1. Field of the Invention
The present invention relates to a method for writing data into a non-volatile semiconductor memory cell, and more particularly to a method for writing data into a non-volatile semiconductor memory cell having a floating gate and a control gate and being electrically writable and erasable.
2. Description of the Related Art
As a non-volatile semiconductor memory, a flash memory is known in which data are written or erased by raising or lowering a threshold voltage (Vth) by injecting/discharging electrons into/from a floating gate which is electrically floating. As a method for writing or erasing data in a flash memory cell, a method is generally known in which data are written by injecting channel hot electrons (CHE) into the floating gate, and a lump erasure is carried out block by block or sector by sector by discharging electrons from the floating gate using a Fowler Nordheim (FN) tunnel current.
The operation of writing data is carried out, for example, by applying a voltage of 5V to a drain, 0V to a source, and 10V to a control gate to inject CHE generated near the drain into the floating gate so as to raise the threshold voltage.
Next, a verifying operation is carried out on the memory cell into which data have been written according to the above-described method. Here, if the threshold voltage (Vth) of the memory cell in a written state is to satisfy 5.5V&lt;Vth, the verifying operation after the writing operation is carried out by comparing the threshold voltage of the memory cell with a reference level 5.5V. If it is found, as a result of verification, that the threshold voltage of the memory cell is higher than the reference level, the writing operation is ended. If the threshold voltage is lower than the reference level, the writing operation is performed again.
FIG. 5 is a flowchart showing a writing operation according to a prior art. By repeating these writing and verifying operations, the threshold voltage of every memory cell can be made higher than 5.5V.
The erasing operation is carried out, for example, by applying a voltage of -10V to the control gate, 5V to the source, and letting the drain open to generate an FN tunnel current from the floating gate to the source for discharging electrons so as to lower the threshold voltage. Here, the erasing operation is carried out on a plurality of cells, for example, block by block or sector by sector.
The operation of reading the data is carried out, for example, by applying a voltage of 5V to the control gate, 1V to the drain, and 0V to the source if the threshold voltage after the writing operation is 5.5V or more and the threshold voltage after the erasing operation is 4.5V or less. Here, since the memory cell in an erased state will be in a conductive state and the memory cell in a written state will be in a non-conductive state by the above operation, the states represented by two values "0" and "1" can be differentiated.
As shown above, the operation of the memory cell having two values has been explained. However, for future flash memories, a research is now being made on a multi-valued cell technique allowing one memory cell to have data of plural bits.
For example, as described on pages 62 to 71 of "Large Capacity Flash Memories for which multi-valued and three-dimensional cells are essential", NIKKEI MICRODEVICES, February 1997, a plurality of data can be stored in one memory cell (a multi-valued cell) in a flash memory using a multi-valued cell technique, so that a large storage capacity can be obtained without increasing the chip area.
Hereafter, an operation of writing data into a multi-valued cell will be explained.
Here, explanation of a technique on multi-valued cells having four values (2 bits/cell) will be given as an example. FIG. 4 is a view for explaining the writing operation in a multi-valued cell. As shown in FIG. 4, the data after the writing operation are divided into four threshold voltage (Vth) ranges.
The memory cell is constructed in such a manner that the threshold voltages in the four ranges can be differentiated by setting, for example, the data "11" to be within a range of 0.5V&lt;Vth&lt;3.0V, the data "10" to be within a range of 3.5V&lt;Vth&lt;4.0V, the data "01" to be within a range of 4.5V&lt;Vth&lt;5.0V, and the data "00" to be within a range of 5.5V&lt;Vth. Thus, the data represented by the four values (11, 10, 01, 00) can be written into the memory cell.
The four-valued data can be written by repeating the writing operation and the verifying operation in the same manner as in the operation of writing two-valued data. For example, the writing operation is carried out using CHE by grounding the source and applying a voltage of 10V to the control gate and 5V to the drain, as shown in FIG. 6 which illustrates the method for writing the data "10". Next, a verifying operation is carried out on the memory cell into which the data have been written by the above-described method. In the case of data "10", the verifying operation is carried out by setting the reference level to be 3.5V and comparing the threshold voltage Vth of the memory cell with the reference level. The threshold voltage Vth of the memory cell can be made higher than 3.5V by repeating these writing and verifying operations.
However, according to the multi-valued cell described in the prior art, the ranges of threshold voltages after the writing operation will be narrow as compared with a two-valued cell. As described before, the threshold voltage Vth must be set within a range having a width of 0.5 V or less in the case of data "10" and "01". The writing speed in memory cells vary to some extent because of the process variations of the memory cells or the like, so that the threshold voltages after the writing operation are distributed in a somewhat wide range.
Lines A, B, and C in FIG. 6 illustrate writing operations in three cells having different writing speeds. In the case of line A in FIG. 6, since the threshold voltage is already higher than an upper limit of the threshold voltage, there will be a problem that correct data cannot be read out. A conventional method employed adjustment of writing pulses or writing voltages so that the threshold voltage of the memory cell will not be higher than its upper limit. In order to perform plural small cycles of writing and verifying operations, the control of the writing operations is complicated as compared with two-valued memory cells. Also, if an attempt is made to allow the memory cell to store data of more than four values, the ranges of the threshold voltages will be narrower and the writing operation will be more complicated, rendering it difficult to realize multi-valued cells. Further, even by these writing methods, a cell in which the threshold voltage exceeds its upper limit as shown by line A in FIG. 6 may unexpectedly appear. In such a case, if a redundancy relief of the memory cell is not available, a writing error occurs, leading to output of incorrect data.